The present invention relates, in general, to the field of fibre channel switching technology. More particularly, the present invention relates to a route caching scheme for a receive port in a fibre channel switch.
Fibre Channel is a high performance, serial interconnect standard designed for bi-directional, point-to-point communications between servers, storage systems, workstations, switches, and hubs. It offers a variety of benefits over other link-level protocols, including efficiency and high performance, scalability, simplicity, ease of use and installation, and support for popular high level protocols.
Fibre channel employs a topology known as a “fabric” to establish connections between ports. A fabric is a network of switches for interconnecting a plurality of devices without restriction as to the manner in which the switch can be arranged. A fabric can include a mixture of point-to-point and arbitrated loop topologies.
In Fibre Channel, a channel is established between two nodes where the channel's primary task is to transport data from one point to another at high speed with low latency. The Fibre channel switch provides flexible circuit/packet switched topology by establishing multiple simultaneous point-to-point connections. Because these connections are managed by the switches or “fabric elements” rather than the connected end devices or “nodes”, fabric traffic management is greatly simplified from the perspective of the device.
In a fibre channel switching environment, a shared memory within the switching element is used to store incoming frames bound for a particular exit port. A destination ID (D_ID) value in the frame header identifies the exit port associated with the incoming frame. For multiple data rates, rate matching FIFO's are used to store the frames before transmission out the receiving port.
In prior approaches, shared memory and storage structures required a large rate matching FIFO to support multiple data rates. For example, to buffer a frame that is incoming at twice the rate of the outgoing port, the FIFOs are at least one half the size of the maximum length frame. Since such FIFO's must necessarily be large to accommodate the number of ports that are coupled to shared memory, this approach requires a significant sized FIFO.
Existing architectures for buffer are also inefficient. For example, memory locations may be allocated to a particular frame, but never actually used. Buffers must handle both rate adaptive cases and same-speed cases, and if they use the same read/write method for both cases, memory is wasted. The current invention provides a different read/write methodology depending on the case.